Automatic test equipment provides the ability for semiconductor device manufacturers to test each and every device made. By testing each device, the manufacturer can sort devices having like speeds, and/or separate failed devices from passing devices. In this manner, the manufacturer is able to confidently put fully functioning devices into the marketplace.
Testing a semiconductor device typically involves applying signals to specified pins according to precise timings, and detecting the device outputs in response to the applied signals. The detected output signals are then compared to expected values to determine whether the device operated within a specified range of parameters. Many of the high-level design considerations for a semiconductor tester focus on the manner of applying and detecting signals to and from the device-under-test (DUT).
With this in mind, semiconductor tester architectures usually fall within one of two types, shared resource, or tester-per-pin. In a conventional tester-per-pin architecture, such as that shown in FIG. 1, each tester channel 10 includes separate tester resources for assignment to one pin of a DUT. Those resources include the necessary timing circuitry 12, pattern generation or data circuitry 14, formatting circuitry 16, and pin electronics 18 for applying signals to, or receiving signals from a pin of the DUT 20. A failure processing circuit handles the evaluation of expected test data versus actual data. This architecture is highly desirable when testing complex logic devices that need flexibility in testing the individual device pins.
Shared resource architectures, on the other hand, are most often found in memory testers, where multiple devices are tested simultaneously to maximize throughput and minimize test costs. A conventional shared resource architecture is shown in FIG. 2, illustrating shared resources for a 2048 channel tester. In this example, sixty-four memory devices 40 (each having thirty-two pins) may be tested with, for example, thirty-two copies 40 of the timing 42, formatting 44, and pattern generation (or data generation) circuitry 46. Fanout circuitry 48 distributes the shared formatted tester signals in parallel to the multiple DUTs 30.
After testing the devices on a shared resource tester, the failure data is typically stored in a bit-image failure memory known as a catchram 50, and subsequently downloaded to redundancy analysis circuitry 52. After the data is analyzed by the redundancy analyzers, a repair solution is sent to a laser repair station 60, along with the failed devices, where the redundant lines identified for use in repairing the device are programmed into operation.
While the conventional shared resource architecture works well for many test applications, and are often far less costly than their per-pin counterparts, different DUTs typically have bits that fail in different rows and/or columns. Consequently, the repair schemes for different devices will be different.
Moreover, some device manufacturers choose to repair devices on the tester without delays inherent in transmitting failure data to separate repair stations. Repairing DUTs on the tester generally involves writing unique repair data after testing to each device to activate internal device fuses corresponding to the desired repair solution. However, without having the ability to write the individual data for each device pin to each device, the device manufacturer cannot repair the devices in this manner. As a result, many manufacturers opt for the more expensive per-pin tester architectures in order to accomplish on-tester device repair.
What is needed and currently unavailable is a low-cost hybrid tester architecture solution that provides the per-pin benefits of unique device failure identification with the shared-resource advantages of low-cost. The hybrid tester architecture of the present invention satisfies these needs.